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Espressif Systems /ESP32-C3 /EFUSE /CLK

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Interpret as CLK

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (EFUSE_MEM_FORCE_PD)EFUSE_MEM_FORCE_PD 0 (MEM_CLK_FORCE_ON)MEM_CLK_FORCE_ON 0 (EFUSE_MEM_FORCE_PU)EFUSE_MEM_FORCE_PU 0 (EN)EN

Description

eFuse clock configuration register.

Fields

EFUSE_MEM_FORCE_PD

Set this bit to force eFuse SRAM into power-saving mode.
MEM_CLK_FORCE_ON

Set this bit and force to activate clock signal of eFuse SRAM.
EFUSE_MEM_FORCE_PU

Set this bit to force eFuse SRAM into working mode.
EN

Set this bit and force to enable clock signal of eFuse memory.

Links

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Register License

Copyright 2024 Espressif Systems (Shanghai) PTE LTD

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License. You may obtain a copy of the License at

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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Register Reference

https://github.com/espressif/svd